Data processing devices employ error correcting codes (ECC) to improve memory reliability. Typically, the ECC code is a set of checkbits calculated for a specified unit of data. The data and associated checkbits are collectively referred to as an ECC word. The number of errors that can be detected and corrected in an ECC word depend on the size of the word, and relative number of data bits and checkbits. For example, a 72 bit ECC word having 64 data bits and 8 checkbits is sufficient to detect any two bits in error, and sufficient to correct any single bit in error.
Each ECC word is typically stored in a memory module having multiple memory devices, whereby each memory device stores a portion of the ECC word. Failure of a memory device will therefore cause errors in the portion of the ECC word stored at the failed device. Accordingly, an increase in the size of memory devices can cause a commensurate increase in the number of bits in error in an ECC word resulting from a device failure. Although the increased impact can be addressed by increasing the size of the ECC word, the size increase could result in an undesirable change to the memory architecture (requiring, for example, an undesirable increase in bus width).
One technique to provide a larger ECC word is to “gang” memory channels, whereby two physical memory channels associated with different memory modules are combined into a single logical memory channel. In this arrangement, each access to memory results in parallel accesses to the two physical memory channels. The two physical memory channels thereby provide a larger ECC word than a single physical memory channel. However, ganging of memory channels can cause an undesirable impact in memory bandwidth due to inefficiencies of memory devices in supporting small burst lengths, sometimes referred to as the “burst chop” penalty. In addition, ganging of memory channels is difficult in data processing devices having an odd number of physical memory channels.